1. Technical Field
The present invention relates to a multi-processor computer system.
2. Description of Related Art
Multi-processor computer systems which provide increased processing power through parallel processing operation are known. Such systems are used in a wide variety of applications such as, for example, flight simulators wherein simulator functions are allocated to different processors. For instance, one known flight simulator system comprises a number of commercial "off-the-shelf" single board computer (SBC) real-time TARGETS each based on a Motorola PowerPC microprocessor, connected to a Data Processing HOST comprising of another Motorola PowerPC SBC. In this system, the HOST and TARGETS are interconnected by a VME 32-bit bus system which is one of a number of known multi-processor bus systems. PowerPC CPUs are used because commercial avionics simulation code is big-endian and thus cannot be run on an Intel x86 processor (or clone).
In more detail, each single board computer comprises a PowerPC microprocessor with associated non-volatile programme memory, system memory (DRAM), and level 2 cache memory, interconnected by a standard PowerPC local bus. A bridge is provided from the PowerPC local bus to an on-board peripheral expansion bus, complying with the Peripheral Component Interconnect (PCI) bus standard. Control of memory systems on the PowerPC local bus as well as the bridge between PowerPC local bus and PCI bus is provided by a Motorola MPC105/6 PCI Bridge/Memory Controller. Connected to the PCI bus arc ethernet and graphics adapters and an SCSI-2 interface (an industry standard Small Computer System Interface providing for the connection of a variety of peripheral devices). An ISA (Industry Standard Architecture) bus is connected to the PCI bus via a PCI-ISA bridge and provides facilities for the interconnection of I/O devices such as mouse, keyboard, floppy drives and serial ports. A further bridge provides connection from the PCI bus to the off-board (backplane) VME bus for communication between SBC's.
Full technical specifications are readily available for all the above mentioned components and bus architectures.
Whilst this known flight simulator system has the benefit that it is constructed from readily available commercial-off-the-shelf components, it does have a number of disadvantages. Limitations to the clock rate and bandwidth of the VME bus are such that inter-processor communication via the VME bus is significantly slower than the intra-processor performance and thus the VME bus presents a communications bottle-neck. In addition, VME based systems present scalability problems since the bus may be saturated by a relatively small number of processors. One means of increasing the total number of available interconnected processors is to employ multiple VME sub-systems, together with some means of communicating between sub-systems, typically some form of reflective memory. Such a system can be designed in such a way that the majority of inter-processor communication remains within a sub-system, and has no impact on other sub-systems, whilst the reflective memory system provides communication between sub-systems when required. This approach however is relatively expensive in terms of the additional VME packaging hardware, support hardware and the reflective memory system required.